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| d a t a sh eet product speci?cation supersedes data of 1999 aug 10 file under integrated circuits, ic12 2000 feb 11 integrated circuits pcf8531 34 128 pixel matrix driver
2000 feb 11 2 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 contents 1 features 2 applications 3 general description 4 packages 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 oscillator 8.2 power-on reset 8.3 i 2 c-bus controller 8.4 input filters 8.5 display data ram 8.6 timing generator 8.7 address counter 8.8 display address counter 8.9 command decoder 8.10 bias voltage generator 8.11 v lcd generator 8.12 reset 8.13 power-down 8.14 column driver outputs 8.15 row driver outputs 8.16 lcd waveforms and ddram to data mapping 8.17 addressing 8.18 instructions 8.18.1 reset 8.18.2 function set 8.18.3 set y address 8.18.4 set x address 8.18.5 set multiplex rate 8.18.6 display control (d, e and im) 8.18.7 set bias system 8.18.8 lcd bias voltage 8.18.9 set v op value: 8.18.10 voltage multiplier control s[1:0] 8.18.11 temperature compensation 9i 2 c-bus interface 9.1 characteristics of the i 2 c-bus 9.1.1 bit transfer 9.1.2 start and stop conditions 9.1.3 system configuration 9.1.4 acknowledge 9.2 i 2 c-bus protocol 9.3 command decoder 10 limiting values 11 handling 12 dc characteristics 13 ac characteristics 14 application information 15 bonding pad locations 16 device protection diagram 17 tray information 18 definitions 19 life support applications 20 purchase of philips i 2 c components 2000 feb 11 3 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 1 features single-chip lcd controller/driver 34 row and 128 column outputs display data ram 34 128 bits 128 icons (last row is used for icons) fast mode i 2 c-bus interface (400 kbit/s) software selectable multiplex rates: 1 : 17, 1 : 26 and1:34 icon mode with mux rate 1 : 2: C featuring reduced current consumption while displaying icons only. on-chip: C generation of v lcd (external supply also possible) C selectable linear temperature compensation C oscillator requires no external components (external clock also possible) C generation of intermediate lcd bias voltages C power-on reset. no external components required software selectable bias configuration logic supply voltage range v dd1 to v ss1 1.8 to 5.5 v supply voltage range for on-chip voltage generator v dd2 and v dd3 to v ss1 and v ss2 2.5 to 4.5 v display supply voltage range v lcd to v ss : C normal mode 4 to 9 v C icon mode 3 to 9 v. low power consumption, suitable for battery operated systems cmos compatible inputs manufactured in silicon gate cmos process. 2 applications telecommunication systems automotive information systems point-of-sale terminals instrumentation. 3 general description the pcf8531 is a low power cmos lcd row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17, 1 : 26 and 1 : 34. furthermore, it can drive up to 128 icons. all necessary functions for the display are provided in a single chip, including on-chip generation of v lcd and the lcd bias voltages, resulting in a minimum of external components and low power consumption. the pcf8531 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (i 2 c-bus). all inputs are cmos compatible. remark : the icon mode is used to save current. when only icons are displayed, a much lower operating voltage (v lcd ) can be used and the switching frequency of the lcd outputs is reduced. in most applications it is possible to use v dd as v lcd . 4 packages the pcf8531 is available as chip with bumps in tray. 5 ordering information type number package name description version pcf8531u/2 - chip with bumps in tray - 2000 feb 11 4 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 6 block diagram handbook, full pagewidth mgs465 display data ram matrix data ram data latches matrix latches column drivers c0 to c127 pcf8531 r0 to r33 row drivers command decoder address counter display address counter timing generator oscillator internal reset power-on reset enr res osc i 2 c-bus control input filters sa0 scl sda sdack v lcdout v lcdsense v lcdin t4 t3 t2 t1 34 v ss2 v ss1 v dd1 v dd2 v dd3 v lcd generator bias voltage generator 128 fig.1 block diagram. 2000 feb 11 5 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 7 pinning symbol pad description 1 to 14 dummy pads osc 15 oscillator input; note 1 v lcdsense 16 voltage multiplier regulation input (v lcd ); note 2 v lcdout 17 to 23 voltage multiplier output (v lcd ); note 3 v lcdin 24 to 30 lcd supply voltage (v lcd ); note 2 res 31 external reset input (active low); note 4 v dd3 32 to 34 supply voltage 3; note 5 v dd2 35 to 42 supply voltage 2; note 5 v dd1 43 to 49 supply voltage 1; note 5 sda 50 and 51 serial data line input of the i 2 c-bus sdack 52 serial data acknowledge output; note 6 53 dummy pad sa0 54 i 2 c-bus slave address input; bit 0 enr 55 enable internal power-on reset input; note 7 t4 56 test 4 input; note 8 v ss2 57 to 63 ground 2; note 9 v ss1 64 to 70 ground 1; note 9 t3 71 test 3 input; note 8 t1 72 test 1 input; note 8 scl 73 and 74 serial clock line input of the i 2 c-bus 75 to 77 dummy pads t2 78 test 2 output; note 10 79 to 86 dummy pads r0 87 lcd row driver output r2 88 lcd row driver output r4 89 lcd row driver output r6 90 lcd row driver output r8 91 lcd row driver output r10 92 lcd row driver output r12 93 lcd row driver output r14 94 lcd row driver output r16 95 lcd row driver output r18 96 lcd row driver output r20 97 lcd row driver output r22 98 lcd row driver output r24 99 lcd row driver output r26 100 lcd row driver output r28 101 lcd row driver output r30 102 lcd row driver output r32 103 lcd row driver output 2000 feb 11 6 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 notes 1. if the on-chip oscillator is used, this input must be connected to v dd1 . 2. if the internal v lcd generation is used, v lcdout , v lcdin and v lcdsense must be connected together. 3. if an external v lcd is used in the application, then pin v lcdout must be left open circuit, otherwise the chip will be damaged. 4. if only the internal power-on reset is used, this input must be connected to v dd1 . 5. v dd1 is for the logic supply, v dd2 , and v dd3 are for the voltage multiplier. for split power supplies, v dd2 and v dd3 must be connected together. if only one supply voltage is available, v dd1, v dd2 and v dd3 must be connected together. 6. serial data acknowledge for the i 2 c-bus. by connecting sdack to sda externally, the sda line becomes fully i 2 c-bus compatible. having the acknowledge output separated from the serial data line is advantageous in chip-on-glass (cog) applications. in cog applications where the track resistance from the sdack pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. it is possible that the pcf8531 will not be able to create a valid logic 0 level during the acknowledge cycle. by splitting the sda input from the sdack output, the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdack pad to the system sda line to guarantee a valid low level. 7. if enr is connected to v ss , power-on reset is disabled; to enable power-on reset enr should be connected to v dd1 . 8. in the application, this input must be connected to v ss . 9. v ss1 and v ss2 must be connected together. 10. in the application, t2 must be left open circuit. c0 to c127 104 to 231 lcd column driver outputs r33 232 lcd row driver output; icon row r31 233 lcd row driver output r29 234 lcd row driver output r27 235 lcd row driver output r25 236 lcd row driver output r23 237 lcd row driver output r21 238 lcd row driver output r19 239 lcd row driver output r17 240 lcd row driver output r15 241 lcd row driver output r13 242 lcd row driver output r11 243 lcd row driver output r9 244 lcd row driver output r7 245 lcd row driver output r5 246 lcd row driver output r3 247 lcd row driver output r1 248 lcd row driver output symbol pad description 2000 feb 11 7 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 8 functional description 8.1 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required and the osc input must be connected to v dd . an external clock signal, if used, is connected to this input. 8.2 power-on reset the on-chip power-on reset initializes the chip after power-on or power failure. 8.3 i 2 c-bus controller the i 2 c-bus controller receives and executes the commands. the pcf8531 acts as an i 2 c-bus slave receiver and therefore cannot control bus communication. 8.4 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass filters are provided on the sda and scl lines. 8.5 display data ram the pcf8531 contains a 34 128 bits static ram, which stores the display data. the ram is divided into 6 banks of 128 bytes (6 8 128 bits). bank 6 is used for icon data. during ram access, data is transferred to the ram via the i 2 c-bus interface. there is a direct correspondence between the x address and column output number. 8.6 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data buses. 8.7 address counter the address counter sets the addresses of the display data ram for writing. 8.8 display address counter the display address counter generates the addresses for read out of the display data. 8.9 command decoder the command decoder identifies command words that arrive on the i 2 c-bus and determines the destination for the following data bytes. 8.10 bias voltage generator the bias voltage generator generates four buffered intermediate bias voltages. this block contains the generator for the reference voltages and the four buffers. this block can operate in two voltage ranges: normal mode; 4.0 to 9.0 v power save mode; 3.0 to 9.0 v. 8.11 v lcd generator the v lcd voltage generator contains a configurable 2 to 5 times voltage multiplier; this is software programmable. 8.12 reset the pcf8531 has the possibility of two reset modes, internal power-on reset or external reset ( res). the reset mode is selected using the enr signal. after a reset, the chip has the following state: all row and column outputs are set to v ss (display off) ram data is undefined power-down mode. 8.13 power-down during power-down, all static currents are switched off (no internal oscillator, no timing and no lcd segment drive system), and all lcd outputs are internally connected to v ss . the i 2 c-bus function remains operational. 8.14 column driver outputs the lcd drive section includes 128 column outputs (c0 to c127) which should be connected directly to the lcd. the column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. when less than 128 columns are required, the unused column outputs should be left open circuit. 8.15 row driver outputs the lcd drive section includes 34 row outputs (r0 to r33), which should be connected directly to the lcd. the row output signals are generated in accordance with the selected lcd drive mode. if less than 34 rows or lower mux rates are required, the unused outputs must be left open circuit. the row signals are interlaced i.e. the selection order is r0, r2, ..., r1, r3 etc. 2000 feb 11 8 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 8.16 lcd waveforms and ddram to data mapping the lcd waveforms and the ddram to display data mapping are shown in figs 2, 3 and 4. mgs466 row 0 r0 (t) row 2 r2 (t) col 0 c0 (t) col 1 c1 (t) 0 v 0 v v 3 - v ss frame n frame n + 1 0246 8... 1 3 5 7... ... 33 ... 32 0246 8... 1 3 5 7... ... 33 ... 32 v state1 (t) v state1 (t) v state2 (t) v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v lcd - v 2 v 4 - v 5 v ss - v 5 v 4 - v lcd v 3 - v 2 - v lcd 0 v 0 v v 3 - v ss v state2 (t) v lcd v lcd - v 2 v 4 - v 5 v 4 - v lcd v 3 - v 2 v ss - v 5 - v lcd fig.2 typical lcd driver waveforms. v state1 (t) = c1(t) - r0(t). v state2 (t) = c1(t) - r2(t). 2000 feb 11 9 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 mgs467 row 0 to 32 row 33 col 1 on/off col 2 off/on col 3 on/on col 4 off/off frame n frame n + 1 v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss only icons are driven fig.3 icon mode; mux 1 : 2 lcd waveforms. 2000 feb 11 10 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 top of lcd mgs468 bank 0 bank 1 bank 2 bank 3 bank 4 r32 r24 r16 r8 r0 r33 (icon row) bank 5 lcd ddram fig.4 ddram to display mapping. 2000 feb 11 11 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 8.17 addressing data is written in bytes into the ram matrix of the pcf8531 as illustrated in figs 5, 6 and 7. the display ram has a matrix of 34 128 bits. the columns are addressed by the address pointer. the address ranges are x 0 to x 127 (7fh) and y 0 to y 5 (5h). addresses outside of these ranges are not allowed. in vertical addressing mode (v = 1), the y address increments after each byte (see fig.6). after the last y address (y = 4), y wraps around to 0 and x increments to address the next column. in horizontal addressing mode (v = 0), the x address increments after each byte (see fig.7). after the last x address (x = 127), x wraps around to 0 and y increments to address the next row. after the very last address (x = 127 and y = 4), the address pointers wrap around to address (x = 0 and y = 0). it should be noted that in bank 4 only the lsb (db0) of the data will be written into the ram. the y address 5 is reserved for icon data and is not affected by the addressing mode; it should be noted that in bank 5 only the 5th data bit (db4) will be written into the ram. handbook, full pagewidth mgs469 0 1 2 3 5 4 0 127 x address icon data y address lsb msb lsb msb lsb msb fig.5 ram format and addressing. handbook, full pagewidth mgs470 05 16 2 3 4 0 1 icon data 0 1 2 3 4 5 638 639 0 127 x address y address fig.6 sequence of writing data bytes into ram with vertical addressing (v = 1). 2000 feb 11 12 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 handbook, full pagewidth mgs471 012 128 129 130 256 257 258 384 385 386 512 513 514 0 1 icon data 0 1 2 3 4 5 127 255 383 511 639 0 127 x address y address fig.7 sequence of writing data bytes into ram with horizontal addressing (v = 0). 8.18 instructions only two pcf8531 registers, the instruction register (ir) and the data register (dr) can be directly controlled by the mpu. before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of mpus which operate at different speeds or to allow interfacing to peripheral control ics. the pcf8531 operation is controlled by the instructions given in table 1. details are explained in subsequent sections. instructions are of four types: 1. those that define pcf8531 functions such as display configuration, etc. 2. those that set internal ram addresses 3. those that perform data transfer with internal ram 4. others. in normal use, category 3 instructions are used most frequently. automatic incrementing by 1 of internal ram addresses after each data write reduces the mpu program load. 8.18.1 r eset after reset or internal power-on reset (depending on application), the lcd driver will be set to the following state: power-down mode (pd = 1) horizontal addressing (v = 0) display blank (d = 0; e = 0), no icon mode (im = 0) address counter x[6:0] = 0; y[2:0] = 0 bias system bs[2:0] = 0 multiplex rate m[1:0] = 0 (mux rate 1 : 17) temperature control mode tc[2:0] = 0 hv-gen control, hve = 0 the hv generator is switched off, prs = 0 and s[1:0] = 0 v lcd =0v ram data is undefined command page definition h[1:0] = 0. 2000 feb 11 13 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 8.18.2 f unction set 8.18.2.1 pd when pd = 1, the power-down mode of the lcd driver is active: all lcd outputs at v ss (display off) power-on reset detection active, oscillator off v lcd can be disconnected i 2 c-bus is operational, commands can be executed ram contents not cleared; ram data can be written register settings remain unchanged. 8.18.2.2 v when v = 0 the horizontal addressing is selected. the data is written into the ddram as shown in fig.7. when v = 1 the vertical addressing is selected. the data is written into the ddram as shown in fig.6. icon data is written independently of v when y address is 5. 8.18.3 s et y address bits y 2 ,y 1 and y 0 define the y address vector of the display ram. table 1 y address 8.18.4 s et x address the x address points to the columns. the range of x is 0 to 127 (7fh). 8.18.5 s et multiplex rate m[1:0] selects the multiplex rate (see table 8). 8.18.6 d isplay control (d, e and im) bits d and e select the display mode (see table 6). bit im sets the display to icon mode. 8.18.7 s et bias system different multiplex rates require different bias settings. these are programmed by bs[2:0], which sets the binary number n. the optimum value for n is given by supported values of n are given in table 2. table 3 shows the intermediate bias voltages. y 2 y 1 y 0 bank 0000 0011 0102 0113 1004 1 0 1 5 (icons) n mux rate 3 C = table 2 programming the required bias system bs[2] bs[1] bs[0] n bias system comment 0007 1 11 0016 1 10 0105 1 9 0114 1 8 1003 1 7 recommended for 1 : 34 1012 1 6 recommended for 1 : 26 1101 1 5 recommended for 1 : 17 1110 1 4 recommended for icon mode 2000 feb 11 14 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 8.18.8 lcd bias voltage table 3 intermediate lcd bias voltages 8.18.9 s et v op value : the operating voltage v lcd can be set by software. the voltage at reference temperature [v lcd (t = t cut )] can be calculated as: v lcd (t cut )=(a+v op b). the generated voltage is dependent on the temperature, programmed temperature coefficient (tc) and the programmed voltage at reference temperature (t cut ). v lcd =v lcd (t cut ) [1+tc (t - t cut )]. the parameter values are given in table 4. two overlapping v lcd ranges can be selected via the command hv-gen control (see table 4 and fig.8). the maximum voltage that can be generated depends on the v dd2 and v dd3 voltages and the display load current. for mux 1 : 34, the optimum operating voltage of the liquid can be calculated as: where v th is the threshold voltage of the liquid crystal material used. the practical value for v op is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd , the user has to ensure, while setting the v op register and selecting the temperature compensation, that the v lcd limit of maximum 9 v will never be exceeded under all conditions and including all tolerances. symbol bias voltages example for 1 7 bias v1 v lcd v lcd v2 6 7 v lcd v3 5 7 v lcd v4 2 7 v lcd v5 1 7 v lcd v6 v ss v ss n3 + n4 + ------------ - v lcd n2 + n4 + ------------ - v lcd 2 n4 + ------------ - v lcd 1 n4 + ------------ - v lcd v lcd 134 + 21 1 34 ---------- C ? ?? --------------------------------------- v th 5.30 v th == table 4 parameter values for the hv generator programming symbol value unit prs=0 prs=1 t cut 27 27 c a 2.94 6.75 v b 0.03 0.03 v programming range 2.94 to 6.75 6.75 to 10.56 v 2000 feb 11 15 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 handbook, full pagewidth mgl935 00 01 02 a v lcd 03 04 05 06 . . . 7d 7e 7f 00 01 02 03 04 05 06 . . . 5f 6f 7f b low high fig.8 v op programming of pcf8531. v op [6:0] (programmed) [00h to 7fh] programme range low and high. 8.18.10 v oltage multiplier control s[1:0] the pcf8531 incorporates a software configurable voltage multiplier. after reset (internal or external), the voltage multiplier is set to 2 v dd2 . the voltage multiplier factors are set via the command hv-gen configuration (see tables 4, 5 and 6). 8.18.11 t emperature compensation due to the temperature dependency of the liquid crystals viscosity, the lcd controlling voltage v lcd should usually be increased at lower temperatures to maintain optimum contrast. figure 9 shows v lcd for high multiplex rates. linear temperature compensation is supported in the pcf8531. the temperature coefficient of v lcd can be selected from eight values by setting bits tc[2:0] (see tables 4, 5 and 6). handbook, halfpage mgs473 t v lcd 0 c fig.9 v lcd as a function of liquid crystal temperature. 2000 feb 11 16 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 table 5 instruction set note 1. r/ w is set in the slave address byte; co and rs are set in the control byte. instruction i 2 c-bus command (1) i 2 c-bus command byte description rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 h 1 and h 0 = dont care (h independent command page) nop 0 0 00000000no operation write data 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 write data to display ram set default h[1:0] 0 0 0 0000001 select h[1:0] = 0 h 1 = 0 and h 0 = 0 (function and ram command page) instruction set 0 0 0 00010h1h0 select command page function set 0 0 0 0100pdv0pow er-down control; entry mode set y address of ram 0 0 01000y 2 y 1 y 0 set y address of ram; 0 y 5 set x address of ram 001x 6 x 5 x 4 x 3 x 2 x 1 x 0 set x address part of ram; 0 x 127 h 1 = 0 and h 0 = 1 (display setting command page) multiplex rate 0 0 0 00001m1m0 select multiplex rate display control 0 0 0 0001dime set display con?guration bias system 0 0 0 0010bs 2 bs 1 bs 0 set bias system (bsx) h 1 = 1 and h 0 = 0 (hv-gen command page) hv-gen control 0 0 0 00001prshve set v lcd programming range hv-gen con?guration 0 0 000010s1s0 set voltage multiplication factor temperature control 0 0 0 0100tc 2 tc 1 tc 0 set temperature coef?cient test modes 0 0 0 1 x xxxxxdo not use (reserved for test) v lcd control 0 0 1 v op6 v op5 v op4 v op3 v op2 v op1 v op0 set v lcd register 0 v op 127 2000 feb 11 17 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 table 6 explanations for symbols in table 5 note 1. the h-bits identify the command page (use set default h[1:0] command to set h[1:0] = 0. bit 0 1 pd chip is active chip is in power-down mode v horizontal addressing vertical addressing im normal mode; full display + icons icon mode; only icons are displayed h[1:0] (1) see table 7 d and e see table 7 hve voltage multiplier disabled voltage multiplier enabled prs v lcd programming range low v lcd programming range high tc[2:0] see table 7 s[1:0] see table 7 table 7 description of bits h, d and e, tc and s table 8 multiplex rates bits value description command page (h) h[1:0] 00 function and ram command page 01 display setting command page 10 hv-gen command page display modes (d, e) d and e 00 display blank 10 normal mode 01 all display segments 11 inverse video mode temperature coef?cient (tc) tc[2:0] 000 temperature coef?cient 0 001 temperature coef?cient 1 010 temperature coef?cient 2 011 temperature coef?cient 3 100 temperature coef?cient 4 101 temperature coef?cient 5 110 temperature coef?cient 6 111 temperature coef?cient 7 voltage multiplier factor (s) s[1:0] 00 2 voltage multiplier 01 3 voltage multiplier 10 4 voltage multiplier 11 5 voltage multiplier mux rate m1 m0 1:17 0 0 1:26 1 0 1:34 0 1 2000 feb 11 18 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 9i 2 c-bus interface 9.1 characteristics of the i 2 c-bus the i 2 c-bus is for bi-directional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1.1 b it transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see fig.10). 9.1.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). the start and stop conditions are illustrated in fig.11. 9.1.3 s ystem configuration the system configuration is illustrated in fig.12 transmitter: the device that sends the data to the bus receiver: the device that receives the data from the bus master: the device that initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. 9.1.4 a cknowledge acknowledge on the i 2 c-bus is illustrated in fig.13. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high signal put on the bus by the transmitter, during which time the master generates an extra acknowledge related clock pulse. a slave receiver that is addressed must generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge- related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig.10 bit transfer. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl 2000 feb 11 19 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 fig.11 definition of start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.12 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.13 acknowledge on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 2000 feb 11 20 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 9.2 i 2 c-bus protocol this driver does not support read. the pcf8531 is a slave receiver. therefore, it only responds when r/ w=0 in the slave address byte. before any data is transmitted on the i 2 c-bus, the device that should respond is addressed first. two 7-bit slave addresses (0111100 and 0111101) are reserved for the pcf8531. the least significant bit of the slave address is set by connecting the input sa0 to either logic 0 (v ss ) or logic 1 (v dd ). the i 2 c-bus protocol is illustrated in fig.14. the sequence is initiated with a start condition (s) from the i 2 c-bus master, and is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, all others ignore the i 2 c-bus transfer. after acknowledgement, one or more command words follow, which define the status of the addressed slaves. a command word consists of a control byte, which defines co and rs, plus a data byte (see fig.14 and table 1). the last control byte is tagged with a cleared most significant bit, the continuation bit co. the control and data bytes are also acknowledged by all addressed slaves on the bus. after the last control byte, depending on the rs bit setting, either a series of display data bytes or command data bytes may follow. if the rs bit was set to logic 1, these display bytes are stored in the display ram at the address specified by the data pointer. the data pointer is automatically updated and the data is directed to the intended pcf8531 device. if the rs bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. the acknowledgement after each byte is made only by the addressed pcf8531. at the end of the transmission, the i 2 c-bus master issues a stop condition (p). 9.3 command decoder pairs of bytes; information in the second byte, the first byte determines whether information is display or instruction data stream of information bytes after co = 0; display or instruction data, depending on last rs (register selection). the command decoder identifies command words that arrive on the i 2 c-bus. the most significant bit of a control byte is the continuation bit co. if this bit is logic 1, it indicates that only one data byte (either command or ram data) will follow. if this bit is logic 0, it indicates that a series of data bytes (either command or ram data) may follow. the db6 bit of a control byte is the ram data/command bit rs. when this bit is at logic 1, it indicates that another ram data byte will be transferred next. if the bit is at logic 0, it indicates that another command byte will be transferred next. handbook, full pagewidth mgs474 s011110sa0 a slave address r/w corsxxxxxx control byte fig.14 slave address and control byte. 2000 feb 11 21 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 handbook, full pagewidth mgs475 s011110 s a 0 0a acknowledge from pcf8531 acknowledge from pcf8531 acknowledge from pcf8531 acknowledge from pcf8531 acknowledge from pcf8531 1 control byte a data byte data byte n 3 0 bytes 1 byte slave address msb . . . . . . . . . . . lsb 2n 3 0 bytes a co co 0a ap rs r/w control byte rs fig.15 master transmits to slave receiver; write mode. 10 limiting values in accordance with the absolute maximum rating system (iec 134); note 1. note 1. parameters are valid over the operating temperature range unless otherwise specified. all voltages referenced to v ss unless otherwise noted. 11 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is recommended to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd1 logic supply voltage - 0.5 +5.5 v v dd2, v dd3 multiplier supply voltage - 0.5 +4.5 v i dd supply current - 50 +50 ma v lcd lcd supply voltage - 0.5 +9.0 v i lcd lcd supply current - 50 +50 ma i ss negative supply current - 50 +50 ma v i /v o input/output voltage (any input/output) - 0.5 v dd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma p tot total power dissipation per package - 300 mw p/out power dissipation per output - 30 mw t stg storage temperature - 65 +150 c t j junction temperature - 150 c 2000 feb 11 22 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 12 dc characteristics v dd1 = 1.8 (1.9) to 5.5 v; v dd2 and v dd3 = 2.5 to 4.5 v; v ss1,2 =0v; v dd1 to v dd3 v lcd 9.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v lcd lcd supply voltage note 1 4.0 - 9.0 v icon mode; note 1 3.0 - 9.0 v v dd1 logic supply voltage 1.9 - 5.5 v t amb 3- 25 c 1.8 - 5.5 v v dd2, v dd3 multiplier supply voltage lcd voltage internally generated 2.5 - 4.5 v i dd supply current power-down mode; internal v lcd - 210 m a normal mode; internal v lcd ; notes 2 and 3 - 170 350 m a normal mode; external v lcd ; note 2 - 10 50 m a i lcd lcd input current normal mode; external v lcd ; notes 2 and 4 - 25 100 m a icon mode; external v lcd ; notes 2 and 5 - 15 70 m a v por power-on reset level note 6 0.9 1.2 1.6 v logic v il low-level input voltage v ss - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd v i ol low-level output current (sda) v ol = 0.4 v; v dd = 5 v 3.0 -- ma i li input leakage current v i =v dd or v ss - 1 - +1 m a column and row outputs r o(col) column output resistance c0 to c127 note 7 - 12 20 k w r o(row) row output resistance r0 to r33 note 7 - 12 20 k w v bias(col) bias tolerance c0 to c127 - 100 0 +100 mv v bias(row) bias tolerance r0 to r33 - 100 0 +100 mv 2000 feb 11 23 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 notes 1. as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd , the user has to ensure, while setting the v op register and selecting the temperature compensation, that the v lcd limit of maximum 9 v will never be exceeded under all conditions and including all tolerances. 2. lcd outputs are open circuit, inputs at v dd or v ss ; bus inactive. 3. v dd1 to v dd3 = 2.85 v; v lcd = 7.0 v; voltage multiplier = 3 v dd ; f osc = 34 khz. 4. v dd1 to v dd3 = 2.75 v; v lcd = 9.0 v; f osc = 34 khz. 5. v dd1 to v dd3 = 2.75 v; v lcd = 3.5 v; f osc = 34 khz. 6. resets all logic when v dd1 2000 feb 11 25 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 fig.17 i 2 c-bus timing diagram. n dbook, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat handbook, halfpage 2345 400 200 100 300 mgs477 i dd ( m a) v dd2 and v dd3 (v) 4 v v lcd = 9 v 7.5 v fig.18 i dd , internal v lcd generation. v dd1 = 2 v; 4 voltage multiplier; t amb =27 c; tc = 0; bs = 100; no v lcd load. handbook, halfpage 246 10 400 200 100 300 mgs478 8 i dd ( m a) v lcd (v) 2 5 4 3 fig.19 i dd for different multiplication factors. v dd1 = 1.8 v; v dd2 and v dd3 = 2.6 v; t amb =27 c; f osc = 34 khz; no v lcd load. 2000 feb 11 26 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 handbook, halfpage - 50 0 50 100 9 7 6 8 mgs479 tc0 tc1 tc6 tc7 v lcd (v) t ( c) fig.20 temperature coefficient. v lcd = 7.5 v; v dd1 to v dd3 = 2.7 v; t amb =27 c; no v lcd load. handbook, halfpage 246 10 30 10 0 20 mgs480 8 i ( m a) v lcd (v) i lcd i dd fig.21 i dd and i lcd with external v lcd . v dd1 = 1.8 v; v dd2 and v dd3 = 2.5 v; external v lcd ; t amb =27 c; tc = 0; bs = 100; no v lcd load. handbook, halfpage 02040 80 30 10 0 20 mgs481 60 i ( m a) f (khz) i lcd i dd fig.22 i dd and i lcd dependent from frequency. v dd1 = 2.5 v; v dd2 and v dd3 = 2.5 v; external v lcd ; t amb =27 c; tc = 0; bs = 100; no v lcd load. handbook, halfpage 3 86 82 84 80 78 3.2 4 mgs482 3.4 3.6 3.8 i dd ( m a) v lcd (v) fig.23 internal v lcd , icon mode. v dd1 = 1.8 v; v dd1 = 2.5 v; 2 voltage multiplier; t amb =27 c; tc = 0; bs = 111; no v lcd load. 2000 feb 11 27 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 14 application information table 9 programming example for pcf8531 step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 1 1 1 0 sa0 0 start; slave address; r/ w=0 2 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 3 0 0 0 0 0 0 0 1 h[1:0] independent command; select function and ram command page (h[1:0] = 00) 4 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 5 0 0 1 0 0 0 1 0 function and ram command page pd = 0 and v = 1 6 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 7 0 0 0 0 1 0 0 1 function and ram command page select display setting command page h[1:0] = 01 8 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 9 0 0 0 0 1 1 0 0 display setting command page; set normal mode (d = 1; im = 0 and e = 0) 10 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 11 0 0 0 0 0 1 0 1 select mux rate 1 : 34 12 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 13 0 0 0 0 0 0 0 1 h[2:0] independent command; select function and ram command page h[1:0] = 00 14 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 15 0 0 0 0 1 0 1 0 function and ram command page; select hv-gen command page h[1:0] = 10 16 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 17 0 0 0 0 1 0 1 1 hv-gen command page; select voltage multiplication factor 5 s[1:0] = 11 18 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 19 0 0 1 0 0 0 1 0 hv-gen command page; select temperature coef?cient 2 tc[2:0] = 010 20 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 2000 feb 11 28 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 21 0 0 0 0 0 1 1 1 hv-gen command page; select high v lcd programming range (prs = 1); voltage multiplier off (hve = 1) 22 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 23 1 0 1 0 0 0 0 0 hv-gen command page; set v lcd = 7.71 v; v op [6:0] = 0100000 24 0 1 0 0 0 0 0 0 control byte; co = 0; rs = 1 25 0 0 0 1 1 1 1 1 data write; y and x are initialized to 0 by default, so they are not set here 26 0 0 0 0 0 1 0 1 data write 27 0 0 0 0 0 1 1 1 data write 28 0 0 0 0 0 0 0 0 data write 29 0 0 0 1 1 1 1 1 data write 30 0 0 0 0 0 1 0 0 data write step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 mgs405 mgs406 mgs407 mgs407 mgs409 mgs410 2000 feb 11 29 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 31 0 0 0 1 1 1 1 1 data write; last data and stop transmission 32 0 1 1 1 1 0 sa0 0 repeated start; slave address; r/ w=0 33 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 34 0 0 0 0 0 0 0 1 h[1:0] independent command; select function and ram command page h[1:0] = 00 35 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 36 0 0 0 0 1 0 0 1 function and ram command page; select display setting command page h[1:0] = 01 37 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 38 0 0 0 0 0 0 0 1 h[1:0] independent command; select function and ram command page h[1:0] = 00 step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 mgs411 mgs411 mgs411 mgs411 mgs411 mgs411 mgs411 mgs411 2000 feb 11 30 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 the pinning of the pcf8531 is optimized for single plane wiring e.g. for chip-on-glass display modules. display size: 34 128 pixels. 39 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 40 0 0 0 0 1 1 0 1 display control; set inverse video mode (d = 1; e = 1 and im = 0) 41 1 0 0 0 0 0 0 0 control byte; co = 1; rs = 0 42 1 0 0 0 0 0 0 0 set x address of ram; set address to 0000000 43 0 1 0 0 0 0 0 0 control byte; co = 0; rs = 1 44 0 0 0 0 0 0 0 0 data write step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 mgs411 mgs412 mgs412 mgs412 mgs412 mgs414 2000 feb 11 31 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 handbook, full pagewidth mgs483 host microprocessor/ microcontroller lcd panel sda v ss1, v ss2 v ss v dd(i2c) v lcd v dd1 to v dd3 v ss1, v ss2 scl sda scl sa0 pcf8531 res sdack r pu r pu res enr 128 column drivers 34 row drivers fig.24 typical system configuration. the host microprocessor/microcontroller and the pcf8531 are both connected to the i 2 c-bus. the sda and scl lines must be connected to the positive power supply via pull-up resistors. the internal oscillator requires no external components. the appropriate intermediate biasing voltage for the multiplexed lcd waveforms are generated on-chip. the only other connections required to complete the system are to the power supplies (v dd ,v ss and v lcd ) and suitable capacitors for decoupling v lcd and v dd . 2000 feb 11 32 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 handbook, full pagewidth mgs484 3 display 34 128 pixels v dd1 to v dd3 i/o v ss1 v ss2 c ext r supply r i/o v lcd pcf8531 128 17 17 fig.25 chip-on-glass application. the required minimum values for the external capacitors in an application with the pcf8531 are as follows: c ext = 100 nf for v lcd and v ss1 and v ss2 , and c ext = 470 nf for v dd1 to v dd3 and v ss1 and v ss2 higher capacitor values are recommended for ripple reduction for cog applications, the recommended ito track resistance is to be minimized for the i/o and supply connections. optimized values for these tracks are below 50 w for the supply (r supply ) and below 100 w for the i/o connections (r i/o ). to reduce the sensitivity of the reset to esd/emc disturbances for a chip-on-glass application, it is strongly recommended to implement a series input resistance in the reset line (recommended minimum value 8 k w ) on the glass (ito). if the reset input is not used, it should be connected to v dd1 using a short connection. 2000 feb 11 33 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 15 bonding pad locations table 10 bonding pad locations all x and y coordinates are referenced to the centre of the chip (dimensions in m m; see fig.28). symbol pad x y dummy 1 +5973.6 - 821.7 dummy 2 +5969.5 +823.4 dummy 3 +5899.5 +823.4 dummy 4 +5829.5 +823.4 dummy 5 +5479.5 +823.4 dummy 6 +5409.5 +823.4 dummy 7 +5059.5 +823.4 dummy 8 +4989.5 +823.4 dummy 9 +4639.5 +823.4 dummy 10 +4569.5 +823.4 dummy 11 +4219.5 +823.4 dummy 12 +4149.5 +823.4 dummy 13 +3799.5 +823.4 dummy 14 +3729.5 +823.4 osc 15 +3449.5 +823.4 v lcdsense 16 +3169.5 +823.4 v lcdout 17 +3099.5 +823.4 v lcdout 18 +3029.5 +823.4 v lcdout 19 +2959.5 +823.4 v lcdout 20 +2889.5 +823.4 v lcdout 21 +2819.5 +823.4 v lcdout 22 +2749.5 +823.4 v lcdout 23 +2679.5 +823.4 v lcdin 24 +2539.5 +823.4 v lcdin 25 +2469.5 +823.4 v lcdin 26 +2399.5 +823.4 v lcdin 27 +2329.5 +823.4 v lcdin 28 +2259.5 +823.4 v lcdin 29 +2189.5 +823.4 v lcdin 30 +2119.5 +823.4 res 31 +1979.5 +823.4 v dd3 32 +1699.5 +823.4 v dd3 33 +1629.5 +823.4 v dd3 34 +1559.5 +823.4 v dd2 35 +1279.5 +823.4 v dd2 36 +1209.5 +823.4 v dd2 37 +1139.5 +823.4 v dd2 38 +1069.5 +823.4 v dd2 39 +999.5 +823.4 v dd2 40 +929.5 +823.4 v dd2 41 +859.5 +823.4 v dd2 42 +789.5 +823.4 v dd1 43 +649.5 +823.4 v dd1 44 +579.5 +823.4 v dd1 45 +509.5 +823.4 v dd1 46 +439.5 +823.4 v dd1 47 +369.5 +823.4 v dd1 48 +299.5 +823.4 v dd1 49 +229.5 +823.4 sda 50 +19.5 +823.4 sda 51 - 50.5 +823.4 sdack 52 - 400.5 +823.4 dummy 53 - 750.5 +823.4 sa0 54 - 820.5 +823.4 enr 55 - 1100.5 +823.4 t4 56 - 1380.5 +823.4 v ss2 57 - 1660.5 +823.4 v ss2 58 - 1730.5 +823.4 v ss2 59 - 1800.5 +823.4 v ss2 60 - 1870.5 +823.4 v ss2 61 - 1940.5 +823.4 v ss2 62 - 2010.5 +823.4 v ss2 63 - 2080.5 +823.4 v ss1 64 - 2220.5 +823.4 v ss1 65 - 2290.5 +823.4 v ss1 66 - 2360.5 +823.4 v ss1 67 - 2430.5 +823.4 v ss1 68 - 2500.5 +823.4 v ss1 69 - 2570.5 +823.4 v ss1 70 - 2640.5 +823.4 t3 71 - 2780.5 +823.4 t1 72 - 3060.5 +823.4 scl 73 - 3410.5 +823.4 scl 74 - 3480.5 +823.4 dummy 75 - 3830.5 +823.4 dummy 76 - 4180.5 +823.4 dummy 77 - 4530.5 +823.4 t2 78 - 4600.5 +823.4 symbol pad x y 2000 feb 11 34 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 dummy 79 - 4880.5 +823.4 dummy 80 - 4950.5 +823.4 dummy 81 - 5230.5 +823.4 dummy 82 - 5300.5 +823.4 dummy 83 - 5650.5 +823.4 dummy 84 - 5720.5 +823.4 dummy 85 - 5930.5 +823.4 dummy 86 - 5926.4 - 821.7 r0 87 - 5786.4 - 821.7 r2 88 - 5716.4 - 821.7 r4 89 - 5646.4 - 821.7 r6 90 - 5576.4 - 821.7 r8 91 - 5506.4 - 821.7 r10 92 - 5436.4 - 821.7 r12 93 - 5366.4 - 821.7 r14 94 - 5296.4 - 821.7 r16 95 - 5226.4 - 821.7 r18 96 - 5156.4 - 821.7 r20 97 - 5086.4 - 821.7 r22 98 - 5016.4 - 821.7 r24 99 - 4946.4 - 821.7 r26 100 - 4876.4 - 821.7 r28 101 - 4806.4 - 821.7 r30 102 - 4736.4 - 821.7 r32 103 - 4666.4 - 821.7 c0 104 - 4526.4 - 821.7 c1 105 - 4456.4 - 821.7 c2 106 - 4386.4 - 821.7 c3 107 - 4316.4 - 821.7 c4 108 - 4246.4 - 821.7 c5 109 - 4176.4 - 821.7 c6 110 - 4106.4 - 821.7 c7 111 - 4036.4 - 821.7 c8 112 - 3966.4 - 821.7 c9 113 - 3896.4 - 821.7 c10 114 - 3826.4 - 821.7 c11 115 - 3756.4 - 821.7 c12 116 - 3686.4 - 821.7 c13 117 - 3616.4 - 821.7 c14 118 - 3546.4 - 821.7 c15 119 - 3476.4 - 821.7 symbol pad x y c16 120 - 3406.4 - 821.7 c17 121 - 3336.4 - 821.7 c18 122 - 3266.4 - 821.7 c19 123 - 3196.4 - 821.7 c20 124 - 3126.4 - 821.7 c21 125 - 3056.4 - 821.7 c22 126 - 2986.4 - 821.7 c23 127 - 2916.4 - 821.7 c24 128 - 2846.4 - 821.7 c25 129 - 2776.4 - 821.7 c26 130 - 2706.4 - 821.7 c27 131 - 2636.4 - 821.7 c28 132 - 2566.4 - 821.7 c29 133 - 2496.4 - 821.7 c30 134 - 2426.4 - 821.7 c31 135 - 2356.4 - 821.7 c32 136 - 2216.4 - 821.7 c33 137 - 2146.4 - 821.7 c34 138 - 2076.4 - 821.7 c35 139 - 2006.4 - 821.7 c36 140 - 1936.4 - 821.7 c37 141 - 1866.4 - 821.7 c38 142 - 1796.4 - 821.7 c39 143 - 1726.4 - 821.7 c40 144 - 1656.4 - 821.7 c41 145 - 1586.4 - 821.7 c42 146 - 1516.4 - 821.7 c43 147 - 1446.4 - 821.7 c44 148 - 1376.4 - 821.7 c45 149 - 1306.4 - 821.7 c46 150 - 1236.4 - 821.7 c47 151 - 1166.4 - 821.7 c48 152 - 1096.4 - 821.7 c49 153 - 1026.4 - 821.7 c50 154 - 956.4 - 821.7 c51 155 - 886.4 - 821.7 c52 156 - 816.4 - 821.7 c53 157 - 746.4 - 821.7 c54 158 - 676.4 - 821.7 c55 159 - 606.4 - 821.7 c56 160 - 536.4 - 821.7 symbol pad x y 2000 feb 11 35 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 c57 161 - 466.4 - 821.7 c58 162 - 396.4 - 821.7 c59 163 - 326.4 - 821.7 c60 164 - 256.4 - 821.7 c61 165 - 186.4 - 821.7 c62 166 - 116.4 - 821.7 c63 167 - 46.4 - 821.7 c64 168 +93.6 - 821.7 c65 169 +163.6 - 821.7 c66 170 +233.6 - 821.7 c67 171 +303.6 - 821.7 c68 172 +373.6 - 821.7 c69 173 +443.6 - 821.7 c70 174 +513.6 - 821.7 c71 175 +583.6 - 821.7 c72 176 +653.6 - 821.7 c73 177 +723.6 - 821.7 c74 178 +793.6 - 821.7 c75 179 +863.6 - 821.7 c76 180 +933.6 - 821.7 c77 181 +1003.6 - 821.7 c78 182 +1073.6 - 821.7 c79 183 +1143.6 - 821.7 c80 184 +1213.6 - 821.7 c81 185 +1283.6 - 821.7 c82 186 +1353.6 - 821.7 c83 187 +1423.6 - 821.7 c84 188 +1493.6 - 821.7 c85 189 +1563.6 - 821.7 c86 190 +1633.6 - 821.7 c87 191 +1703.6 - 821.7 c88 192 +1773.6 - 821.7 c89 193 +1843.6 - 821.7 c90 194 +1913.6 - 821.7 c91 195 +1983.6 - 821.7 c92 196 +2053.6 - 821.7 c93 197 +2123.6 - 821.7 c94 198 +2193.6 - 821.7 c95 199 +2263.6 - 821.7 c96 200 +2403.6 - 821.7 c97 201 +2473.6 - 821.7 symbol pad x y c98 202 +2543.6 - 821.7 c99 203 +2613.6 - 821.7 c100 204 +2683.6 - 821.7 c101 205 +2753.6 - 821.7 c102 206 +2823.6 - 821.7 c103 207 +2893.6 - 821.7 c104 208 +2963.6 - 821.7 c105 209 +3033.6 - 821.7 c106 210 +3103.6 - 821.7 c107 211 +3173.6 - 821.7 c108 212 +3243.6 - 821.7 c109 213 +3313.6 - 821.7 c110 214 +3383.6 - 821.7 c111 215 +3453.6 - 821.7 c112 216 +3523.6 - 821.7 c113 217 +3593.6 - 821.7 c114 218 +3663.6 - 821.7 c115 219 +3733.6 - 821.7 c116 220 +3803.6 - 821.7 c117 221 +3873.6 - 821.7 c118 222 +3943.6 - 821.7 c119 223 +4013.6 - 821.7 c120 224 +4083.6 - 821.7 c121 225 +4153.6 - 821.7 c122 226 +4223.6 - 821.7 c123 227 +4293.6 - 821.7 c124 228 +4363.6 - 821.7 c125 229 +4433.6 - 821.7 c126 230 +4503.6 - 821.7 c127 231 +4573.6 - 821.7 r33 232 +4713.6 - 821.7 r31 233 +4783.6 - 821.7 r29 234 +4853.6 - 821.7 r27 235 +4923.6 - 821.7 r25 236 +4993.6 - 821.7 r23 237 +5063.6 - 821.7 r21 238 +5133.6 - 821.7 r19 239 +5203.6 - 821.7 r17 240 +5343.6 - 821.7 r15 241 +5413.6 - 821.7 r13 242 +5483.6 - 821.7 symbol pad x y 2000 feb 11 36 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 table 11 bonding pads table 12 alignment marks r11 243 +5553.6 - 821.7 r9 244 +5623.6 - 821.7 r7 245 +5693.6 - 821.7 r5 246 +5763.6 - 821.7 r3 247 +5833.6 - 821.7 r1 248 +5903.6 - 821.7 pad size unit pad pitch min. 70 m m pad size; al 62 100 m m bump dimensions 50 90 17.5 ( 5) m m wafer thickness (excluding bumps) 381 m m marks x y c1 - 5402.0 +823.1 c2 +5292.4 +823.4 f +5890.3 +401.9 circle 1 - 5543.0 +798.4 circle 2 +5637.4 +798.4 symbol pad x y handbook, halfpage mgs487 x y 12.23 mm pitch 1.96 mm pcf8531 fig.26 bonding pads. handbook, full pagewidth mgs490 x center c y center 100 m m x center circle y center 100 m m 100 m m 100 m m x center f y center 80 m m fig.27 shapes of recognition pattern. 2000 feb 11 37 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgs486 pad1 t2 t1 t3 scl sda osc res v ss1 v ss2 v lcdin v lcdout v lcdsense v dd1 v dd2 v dd3 enr sa0 sdack pc8531-1 t4 x y 0, 0 c63 . . . . . . c127 . . . c64 . . . c31 . . . c32 . . . r32 . . . c0 . . . r0 . . . c96 c95 . . . r33 . . . r1 . . . fig.28 bonding pad location. the positioning of the bonding pads is not to scale. 2000 feb 11 38 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 16 device protection diagram for all diagrams: the maximum forward current is 5 ma and the maximum reverse voltage is 5 v. handbook, full pagewidth mgs485 v dd1 v dd1 v ss1 v ss2 v ss1 scl, sda, sdack v ss1 v lcdin v ss1 v ss1 v dd1 osc, sa0, t3, t1, t4, res, enr v ss1 v dd1 t2 pads 43 to 49 pads 35 to 42 pads 57 to 63 v dd3 v ss1 pads 32 to 34 v lcdout v ss1 pads 17 to 23 v lcdin (supply), v lcdsense v ss1 pads 16, 24 to 30 pads 87 to 248 pads 73, 74, 50, 51, 52 pads 15, 54, 71, 72, 56, 31, 55 pad 78 pads 64 to 70 pads 57 to 63 v dd2 v ss1 v ss2 fig.29 device protection diagrams. 2000 feb 11 39 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 17 tray information handbook, full pagewidth mgs488 d c a x y f e b fig.30 tray details. the dimensions are given in table 13. table 13 dimensions handbook, halfpage mgs489 pc8531-1 fig.31 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. dim. description value a pocket pitch; x direction 13.72 mm b pocket pitch; y direction 4.17 mm c pocket width; x direction 12.34 mm d pocket width; y direction 2.05 mm e tray width; x direction 50.8 mm f tray width; y direction 50.8 mm x number of pockets in x direction 3 y number of pockets in y direction 10 2000 feb 11 40 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 18 definitions 19 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 20 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2000 feb 11 41 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 notes 2000 feb 11 42 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 notes 2000 feb 11 43 philips semiconductors product speci?cation 34 128 pixel matrix driver pcf8531 notes ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 465006/03/pp 44 date of release: 2000 feb 11 document order number: 9397 750 06616 |
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